1. Field of the Invention
The present invention relates to an apparatus and method for controlling power management.
2. Background of the Related Art
A central processing unit (CPU) has a plurality of power states. In the specification of the Advanced Configuration and Power Interface (ACPI), the power states of the CPU are classified into C0 (working), C1 (auto halt), C2 (sleep), C3 (deep sleep) and C4 (deeper sleep).
The C0 state is defined as a system working state where instructions are executed. The C0 state does not provide a specific power saving.
For the efficient use of power, a CPU in a system generally operates as follows. The system can be changed into an auto halt mode (C1), a sleep mode (C2), a deep sleep mode (C3) and a deeper sleep mode (C4).
The auto halt mode (C1) is a lowest latency state, where software is not affected by a hardware latency state. The sleep mode (C2) and the deep sleep mode (C3) provide more power savings over the auto halt mode (C1) and are executed when no signal is inputted for a predetermined time.
The deeper sleep mode (C4) is a standby mode that is higher than the deep sleep mode (C3). The deeper sleep mode (C4) has a lower voltage than the deep sleep mode (C3) and has the longest latency when changing into the normal operation state. The deeper sleep mode (C4) provides more power savings than the C2 and C3.
FIG. 1 is a block diagram of an apparatus for controlling power management according to the related art. Referring to FIG. 1, a voltage of a CPU 10a must be changed when an operating frequency is changed. Therefore, a VID (voltage identifier) value is transferred to a CPU core DC/DC controller 10b to adjust a voltage applied to the CPU.
That is, the CPU core DC/DC controller 10b receives the VID value from the CPU 10a and outputs a corresponding voltage of a VID table to the CPU 150. The VID table is embedded in the CPU core DC/DC controller 10b of a DC/DC converter.
When the CPU enters the deeper sleep mode (C4), the VID value is not changed, but the voltage is changed. The CPU core DC/DC controller 10b receives the deeper sleep signal (a high active signal) from a South bridge 10c and applies the preset voltage to the CPU 150.
In this case, the deeper sleep mode (C4) is entered/exited at regular intervals. However, an audio noise occurs in capacitors of a power controller 140 included in the DC/DC converter.
The VID is a binary value that allows an output of a voltage corresponding to a frequency. When the CPU changes the frequency, the VID value is transferred to the CPU core DC/DC controller 10b and then the DC/DC converter changes the voltage applied to the CPU.
The related art power management will be described with reference to FIG. 1. A South bridge 10c is used to control a peripheral device and a power supply, and a North bridge (not shown) is used to detect an operating frequency of the CPU 10a. 
The South bridge 10c is connected to the North bridge (not shown) and inputs an enable signal corresponding to the deeper sleep mode (C4) to the CPU core DC/DC controller 10b. At this point, the CPU core DC/DC controller 10b controls the power controller 140 to output a voltage corresponding to the frequency and the deeper sleep mode (C4).
In the deeper sleep mode (C4), the South bridge 10c outputs a high active signal to the CPU core DC/DC controller 10b. Meanwhile, the system is operated so that when the C4 enable signal is inputted, the preset voltage (e.g., 0.748 V) is outputted regardless of the VID value.
The CPU is operated in a plurality of power management modes. In the respective power management modes, the CPU can be separately operated in a high frequency mode (HFM) and a low frequency mode (LFM) depending on the operating frequencies. In the respective operating frequencies, the CPU can also be operated in the power management modes C0, C1, C2, C3 and C4.
In the HFM, an exemplary voltage at a normal mode (C0) equals 1.502 V (VID=1001). Further, in the HFM, an exemplary voltage at a deeper sleep mode (C4) equals 0.748 V (VID=1100)
In this case, for the C4 mode, the deeper sleep signal becomes high and thus the voltage greatly changes from 1.502 V to 0.748 V. Since the voltage changes greatly, a piezoelectric effect occurs in an input ceramic capacitor of the power terminal caused by ripples of the audio frequency band, and thus, a stack plate of the capacitor vibrates. The vibration can also make a printed circuit board (PCB) vibrate, resulting in noise. For these reasons, the C4 mode is inconvenient to users so that its function has been scarcely used.
As described above, related art apparatus and method for operating the C4 mode have various disadvantages. For example, a decoupling ceramic of an output terminal of a CPU recommended by CPU manufacturers (e.g., Intel) vibrates in the deep sleep mode (C3) or deeper sleep mode (C4), resulting in generating noise. However, the C3 mode generates less noise than the C4 mode, and accordingly, it is widely used.
In order to try and remove the noise, the input capacitor of the CPU core power terminal is replaced with a Poscap (one capacitor). However, if all capacitors of the power terminal and the output capacitors are not replaced, the noise cannot be completely removed. Although the complete noise reduction can be achieved by replacing all ceramic capacitors, this causes the increase in the PCB space and the manufacturing cost. For these reasons, most of notebook computers do not support the C4 mode, and thus the lifetime of the battery can be reduced. In addition, the use of the power supply, especially the battery, cannot be efficiently managed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.